1. Field of the Invention
The present invention relates to the semiconductor device and its manufacture method, and more particularly to the semiconductor device which is a CMOS (complementary metal oxide semiconductor) image sensor and its manufacture method.
2. Description of the Related Art
The CMOS image sensors and the CCD (charge-coupled device) image sensors are known widely as the image sensors. Generally, the CMOS image sensors provide poor image quality when compared with the CCD image sensors, but because of low power consumption and small size, the CMOS image sensors are widely used for the portable telephones or the like.
The unit pixel of the CMOS image sensor generally comprises one photo diode and three or four transistors. FIG. 1A shows the unit pixel 110 of the three transistor type CMOS image sensor 100, and FIG. 1B shows the unit pixel 110 of the four transistor type CMOS image sensor 100. The former comprises the photo diode (PD) 120, the source-follower transistor (SF-TR) 130, the selection transistor (SCT-TR) 140, and the reset transistor (RST-TR) 150, and the latter further comprises the transfer transistor (TF-TR) 160.
The PD 120 creates the signal charge by the photoelectric conversion, and the SF-TR 130 transforms the signal charge into the signal voltage. The SCT-TR 140 is used to select the unit pixel 110, the RST-TR 150 is used to reset the PD 120, and the TF-TR 160 is used to transfer the signal charge from the PD 120 to the SF-TR 130.
The PD 120 is connected to the reset voltage line 125 through the RST-TR 150, and the SF-TR 130 is connected to the signal-voltage read-out line 135 through the SCT-TR 140. The SCT-TR 140 is connected to the selection line 145, the RST-TR 150 is connected to the reset line 155, and the TF-TR 160 is connected to the transfer line 165.
In the case of the CMOS image sensor, the N+P junction is used as the photo diode, and it is necessary to suppress junction leak generated in the interface level of the Si/SiO2 oxide-film interface. For this reason, in many cases, by forming the P+shield layer near the surface of the silicon Si substrate, and making it the P+NP embedded diode structure, the Si/SiO2 oxide-film interface and the depletion layer are separated, so that the junction leak is suppressed.
However, there is the problem that it is difficult to separate the Si/SiO2 oxide-film interface and the depletion layer completely. For this reason, in many cases, by performing the H2 annealing in the last stage of the wafer process, the interface level of the Si/SiO2 oxide-film interface created by the damage in the wafer process is reduced, so that the junction leak is suppressed. However, the H2 annealing has the following problem concerning the wiring structure of the CMOS image sensor.
FIG. 2 and FIG. 3 are cross-sectional views showing the principal part of the conventional CMOS image sensor and for explaining the manufacture method. Specifically, FIG. 2 shows the conventional method of forming the multi-layer wiring structure using the CMP (chemical mechanical polishing), and FIG. 3 shows the conventional method of forming the multi-layer wiring structure using the dry etch back.
The left diagrams of each figure show the wiring structure of the 2nd or subsequent layer from the bottom, the right diagrams of each figure show the wiring structure of the 1st layer from the bottom, and the flow of each diagrams A, B, and C is equivalent to the flow of the process of forming the wiring structure.
When aluminum (Al) is used as the material of the wiring layer, as indicated in FIG. 2 C and FIG. 3 C, the wiring structure which is adopted in many cases comprises, from the bottom, the Ti (titanium) film 60, the TiN (titanium nitride) film 65, the aluminum (Al) wiring layer 70, the Ti (titanium) film 80, and the TiN (titanium nitride) film 85 (the thickness of which is, in this order, about 20 nm, about 50 nm, 0.3-1.0 micrometer, about 5 nm, and about 100 nm).
The purpose of the wiring structure is to raise the stress resistance, such as electro-migration, by controlling the crystal stacking tendency of aluminum by the use of Ti. When forming such wiring structure, the CMP may be used as shown in FIGS. 2 A and B, and the dry etch back may be used as shown in FIGS. 3 A and B.
Concerning the 2nd or subsequent layer when using the CMP, as in the left diagram of FIG. 2 A, the inter-layer insulating film 30 of SiO2 is deposited on the lower layer wiring structure 20, and the via hole (window) 21 which penetrates the inter-layer insulating film 30 of SiO2 is formed. The TiN (titanium nitride) film 45 (the thickness is about 50 nm) is deposited on the inter-layer insulating film 30 of SiO2, the W (tungsten) plug layer 50 is embedded in the via hole 21, and the W plug layer 50 is flattened by the CMP as in the left diagram of FIG. 2 B.
Concerning the 1st layer, as in the right diagram of FIG. 2 A, the inter-layer insulating film 30 of SiO2 is deposited on the Si substrate 10 in which the pixels etc. are created, and the contact hole (window) 11 which penetrates the inter-layer insulating film 30 of SiO2 is formed. After the Ti (titanium) film 40 (the thickness about 20 nm) is deposited on the inter-layer insulating film 30 of SiO2, the TiN (titanium nitride) film 45 (the thickness about 50 nm) is deposited, the W (tungsten) plug layer 50 is embedded in the contact hole 11, and the W plug layer 50 is flattened by the CMP as in the right diagram of FIG. 2 B.
If the CMP is used, for either the 1st layer or the 2nd or subsequent layer, the undersurface of the Ti film 60 is exposed to the inter-layer insulating film 30 of SiO2 as in the diagrams of FIG. 2 C. This will adversely affect the H2 annealing. That is, although H2 should pass each inter-layer insulating film of SiO2 and reach the Si/SiO2 oxide-film interface, it will be absorbed by the Ti film 60 in the inter-layer insulating film 30 of SiO2 at the intermediate location.
For this reason, the interface level of the Si/SiO2 oxide-film interface is not fully reduced and the junction leak is not fully suppressed. There is the problem that the quality of image is degraded. This problem is so serious that the area of the undersurface of the Ti film 60 becomes large.
When the dry etch back is used instead of the CMP, concerning the second or subsequent layer as in the left diagram of FIG. 3 B, the portion 46 of the TiN film 45 deposited on the inter-layer insulating film 30 of SiO2 remains without being removed by the dry etch back, and it is avoided that the undersurface of the Ti film 60 is exposed to the inter-layer insulating film 30 of SiO2.
However, concerning the 1st layer as in the right diagram of FIG. 3B, the portion 41 of the Ti film 40 deposited on the inter-layer insulating film 30 of SiO2 also remains without being removed by the dry etch back, and instead of the Ti film 60, the undersurface of the Ti film 40 will be exposed to the inter-layer insulating film 30 of SiO2.
For this reason, the interface level of the Si/SiO2 oxide-film interface is not fully reduced and the junction leak is not fully suppressed. There is the problem that the quality of image is degraded. This problem is so serious that the area of the undersurface of the Ti film 40 becomes large.
Furthermore, concerning either the 1st layer or the 2nd or subsequent layer, there is the problem that the recess 51 of the W plug layer 50 is created by the dry etch back as in the diagram of FIG. 3 B.
In addition, Japanese Patent No. 3021683, Japanese Laid-Open Patent Application No. 07-263546, Japanese Laid-Open Patent Application No. 08-293552, Japanese Laid-Open Patent Application No. 08-340047, Japanese Laid-Open Patent Application No. 09-326490, Japanese Laid-Open Patent Application No. 10-022390, Japanese Laid-Open Patent Application No. 2000-260863, and Japanese Laid-Open Patent Application No. 2002-050595 disclose the background technology relevant to the present invention.